This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-088411, filed Mar. 28, 2000, the entire contents of which are incorporated herein by reference.
This invention relates to a selecting circuit. More particularly, the present invention relates to a selecting circuit to be used for selecting CMOS inverters or constant-current sources in a D/A (digital/analog) converter or an A/D (analog/digital) converter.
Firstly, a D/A converter disclosed in U.S. Pat. No. 5,138,317 will be described as a known D/A converter.
Referring to FIG. 1 of the accompanying drawings, a D/A converter described in the above patent document is adapted to thermometer-decode an n (positive integer)-bit digital data into 2n data (Step A) and convert the 2n data obtained by the thermometer-decoding into 2n data by DWA (data weighted averaging)-decoding (Step B) on the basis of a rearrangement algorithm circuit. Then, the 2n data obtained by the DWA-decoding is used to select CMOS inverters or constant-current sources (Step C).
The DWA-decoding operation is carried out by a selecting circuit (rearrangement algorithm circuit). The selecting circuit selects CMOS inverters or constant-current sources on the basis of a rearrangement algorithm. More specifically, the selecting circuit thermometer-decodes the n-bit data to generate a 2n-valued data (2nxe2x88x921xe2x89xa7mxe2x89xa70) and rearranges the 2n-valued data (by DWA-decoding) on the basis of the rearrangement algorithm so that it selects a total of m CMOS inverters or constant-current sources that are controlled by the selected m lines on the basis of the 2n-valued data. Then, the electric currents of the selected constant-current sources (i) are added (mxc3x97i) and the obtained result is converted into a voltage by an I-V converter circuit to produce the desired analog data.
Now, methods that can be used for selecting CMOS inverters or constant-current sources will be discussed below.
The technique of thermometer-decoding as shown in Table 1 (3 bitsxe2x86x925 values) and Table 2 (3 bitsxe2x86x927 values) is known for selecting CMOS inverters or constant-current sources. This technique is characterized in that a predetermined number of constant-current sources are selected from a side of plurality of constant-current sources that are always arranged side by side like a thermometer for each data conversion.
There is also known a technique of selecting a plurality of constant-current sources with a same probability in order to noise-shaping the errors (noise) in the electric currents that are generated in a plurality of constant-current sources.
Table 3 (3 bitsxe2x86x925 values) and Table 4 (3 bitsxe2x86x927 values) show a selection method referred to as DWA-decoding (data weighted averaging-decoding).
This method is characterized in that constant-current sources are sequentially selected from a side of a plurality of constant-current sources that are arranged side by side to the other side. With this technique, as an operation of data conversion is repeated, constant-current sources are sequentially selected from a side of a plurality of constant-current sources to the other side and, when a constant-current source is selected as one closest to the extremity of the other side, one closest to the extremity of this side is selected so that the selected constant-current sources runs circularly.
FIG. 2 schematically illustrates a first example of D/A converter for converting a 9-valued digital signal into an analog signal. This circuit corresponds to block C of FIG. 1.
A constant-current source 2 adapted to generate an electric current of 4i is connected between a voltage source VDD node and the negative input node of operational amplifier 1. A switch 3 and a constant-current source 4 that are connected in series are connected between the negative input node of operational amplifier 1 and a grounding node. A total of 8 combinations of a switch 3 and a constant-current source 4 are provided and are connected in parallel between the negative input node of the operational amplifier 1 and the grounding node.
The switch circuits 3 are selected by the data obtained by thermometer-decoding or DWA-decoding. The input current of the operational amplifier 1 is defined by the electric current 4i of the constant-current source 2 and the total value of the electric currents i of the constant-current sources 4 that are connected respectively to the selected switch circuits 3. As a result, the operational amplifier performs an I-V conversion to produce an analog data in the form of a voltage. The error (noise) of each of the constant-current sources 4 is subjected to noise-shaping when the technique of DWA-decoding as shown in Tables 3 and 4 is used.
However, U.S. Pat. No. 5,138,317 does not disclose any circuit to be used for DWA-decoding.
Now, a D/A converter disclosed in U.S. Pat. No. 5,404,142 will be described as another known D/A converter.
U.S. Pat. No. 5,404,142 discloses a selecting circuit to be used for DWA-decoding.
The selecting circuit has a configuration as shown in FIGS. 3 and 4.
This selecting circuit can be applied to the D/A converter of FIG. 2. In other words, the D/A converter of FIG. 2 can be made to operate for DWA-decoding by controlling the switch circuit 3 of FIG. 2 by means of a predetermined rearrangement algorithm, while entering DATA 2 of FIG. 3 to the switch circuit 3 of FIG. 2. Then, for example, thermometer-decoded DATA 1 will be rearranged into DATA 2 (by DWA-decoding) by means of this known selecting circuit so that, as a result, constant-current sources 4 will be sequentially and circularly selected.
Thus, the constant-current sources 4 of FIG. 2 will be selected with a same probability and the error (noise) of each of the constant-current sources 4 will be subjected to noise-shaping.
However, it should be noted here that the selecting circuit of FIGS. 3 and 4 comprises a total of twelve switch blocks SB. Therefore, for the circuit of FIG. 2 to perform DWA-decoding operations, the twelve switch blocks SB have to be added thereto. Additionally, as shown in FIG. 4, each of the switch blocks SB comprises three D (delay) type flip-flop circuits (D-FFs), two EX-OR (exclusive OR) gate circuits and two rearrangement gate circuits.
Therefore, a D/A converter as disclosed in U.S. Pat. No. 5,404,142 is accompanied by the problem of involving a complex selecting circuit (hardware) that makes the converter very bulky.
Now, a D/A converter disclosed in U.S. Pat. No. 5,539,403 will be discussed as still another known D/A converter.
The D/A converter described in U.S. Pat. No. 5,539,403 are similar to the above described second known converter in that it is adapted to DWA-decoding. The selecting circuit of the D/A converter is characterized in that it employs a ROM for DWA-decoding. While the rearrangement algorithm is same as that of the selecting circuit of FIGS. 3 and 4, the selecting circuit of this D/A converter is more complex and more bulky than that of the second known converter because of the use of a ROM.
As discussed above, known D/A converters are accompanied by the problem of involving a large selecting circuit (hardware) and consequent high cost when adapted to noise shaping, using DWA-decoding, for achieving highly reliable D/A conversions.
Therefore, it is an object of the present invention to provide a selecting circuit that does not involve the use of bulky hardware for achieving highly reliable D/A conversions at low cost and at a low power consumption rate. Another object of the present invention is to provide a D/A converter and an A/D converter realized by using such a selecting circuit.
According to the invention, the above objects are achieved by providing a selecting circuit comprising a logic circuit, a first signal processing circuit and a second signal processing circuit, the logic circuit being adapted to receive an n-bit (2p+1)-valued (2nxe2x89xa72pxe2x89xa72, n and p being an integer) input signal m (m being an integer satisfying the requirement of 2pxe2x89xa7mxe2x89xa70), generate a pair of internal signals having a value produced by halving the value obtained on the basis of the upper (nxe2x88x921) bits of the input signal m, neglecting the least significant bit of the input signal m, and then, in the case of an input signal m having an odd number value, generate first and second signals by alternately adding 1 to the two internal signals for each input of signal m having an odd number value, the first signal processing circuit having p first output terminals and adapted to select a number of output terminals corresponding to the value of the first signal out of the p first output terminals on the basis of the first signal so as to make the p output terminals to be selected with a same and identical probability of selection, the second signal processing circuit having p second output terminals and adapted to select a number of output terminals corresponding to the value of the second signal out of the p second output terminals on the basis of the second signal so as to make the p output terminals to be selected with a same and identical probability of selection.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.